Decoupling capacitor

ABSTRACT

A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

BACKGROUND Technical Field

The present application relates to integrated electronic circuits, andmore particularly to an integrated circuit equipped with a back-sidedevice protecting the circuit.

Description of the Related Art

Integrated circuits are sometimes subjected to attacks the aim of whichis to determine the structure of the circuit, to modify the operationthereof or to extract confidential information therefrom. An attack maybe carried out from the back side of a circuit equipped on its frontside with components such as capacitors, diodes or transistors, coatedwith conductive tracks. During the attack, a section of the back side isfirst etched, approximately down to level with the wells in which thecomponents are formed. A smaller aperture, for example of 2 μm×2 μmsize, is formed in this section of the back side, approximately down tolevel with active zones and shallow trench isolations (STIs). In thisaperture, cavities are produced, for example by ion beam, these cavitiesextending down to level with the components or conductive tracks on thefront face. Electrical contacts with the components or tracks are thencreated in these cavities, and the pirates use these contacts to analyzethe circuit in operation.

An integrated circuit liable to undergo such an attack may compriseseveral hundred decoupling capacitors. These decoupling capacitors serveto limit the influence of voltage fluctuations on the circuit. Thedecoupling capacitors may occupy more than 20% of the real estate of theintegrated circuit and are, just like the other elements of theintegrated circuit, arranged in cells. These cells are formed between aconductive line at a potential VDD and a conductive line at groundpotential. These lines are generally common to many cells.

FIG. 1 schematically shows from above an example of a capacitor cellforming a decoupling capacitor. The cell comprises a well 2 dopedn-type, depicted by the dashed line, in a substrate 3 that is dopedp-type. A conductive line 4, for example made of polysilicon, is formedon the well 2, with interposition of a dielectric layer (not shown).This conductive line 4 corresponds to a gate line of a MOS transistorand a p-implant is formed in the well 2 using this line 4 by way ofmask.

The cell is placed between conductive supply lines, for example a line 6at a positive voltage VDD and a line 8 at ground potential (GND).Contacts 14 are formed on the line 6 and are connected, by conductivetracks 16, which have been depicted by dashed lines, to contacts 18 withthe zone implanted in the well 2. Likewise, contacts 20 are formed onthe line 8 and are connected, by conductive tracks 22, which have beendepicted by dashed lines, to contacts 24 formed on the line 4 and on thesubstrate 3, connecting them both to ground.

A capacitor is therefore formed between the portion of the well 2located under the conductive line 4 and this conductive line 4.

It is easy to dig holes through these decoupling capacitors withoutdisrupting the operation of the circuit. Specifically, the cellscontaining the decoupling capacitors comprise few key elements andenough space for the passage of contacts. The sites in which thedecoupling capacitors are located therefore run the risk of mostparticularly being targeted by pirates.

It would be desirable to protect decoupling capacitors from attacks ofthe type described above.

BRIEF SUMMARY

Thus, one embodiment provides a decoupling capacitor comprising: twocapacitor cells sharing the same well; a first trench isolation passingthrough the well between the two cells without reaching the bottom ofthe well; and a contact with the well formed in each cell.

According to one embodiment, the cells are placed between two conductivesupply strips, on either side of a central supply strip.

According to one embodiment, the capacitor is formed by the first trenchisolation and by second trench isolations extending in the well in adirection orthogonal to that of the first trench isolation.

According to one embodiment, capacitors comprising a trench isolationare formed in the substrate in which the well is formed.

One embodiment provides an integrated circuit containing a decouplingcapacitor such as described above and a circuit for detecting theimpedance between the contacts with the well in each cell.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These features and advantages, and others, will be described in detailin the following description of particular embodiments, whichdescription is nonlimiting and given with reference to the appendedfigures, in which:

FIG. 1, which was described above, schematically shows a capacitor;

FIGS. 2A and 2B are a top view and a cross-sectional view illustratingone embodiment of two capacitor cells protected from back-side attacks;

FIG. 3 is a top view of an integrated-circuit cell;

FIG. 4A is a more detailed top view of one embodiment of two capacitorcells protected from back-side attacks;

FIGS. 4B to 4D are various cross-sectional views of the cells of FIG.4A; and

FIG. 5 is a schematic of an integrated circuit according to oneembodiment.

DETAILED DESCRIPTION

Elements that are the same have been referenced by the same referencesin the various figures and, in addition, the various figures have notbeen drawn to scale. For the sake of clarity, only those elements thatare useful to the comprehension of the described embodiments have beenshown and are detailed.

In the following description, when reference is made to qualifiers ofposition, such as the terms “front,” “back,” “under.” “horizontal,”“vertical,” etc., reference is being made to the position of theelements in question in the figures. Unless otherwise specified, theexpression “approximately” must be interpreted as meaning to within 10%and preferably to within 5%.

FIGS. 2A and 2B are a top view and a cross-sectional view along the lineB-B of FIG. 2A, showing one embodiment of two capacitor cells, thesecapacitors being protected from back-side attacks. The capacitors arehere, by way of example, capacitors based on trench isolations.

As was described above, each cell is placed between a conductive line ata potential VDD and a conductive line at ground potential (GND). The twocells C1, C2 shown are formed between two conductive lines 6 at thepotential VDD on either side of a conductive line 8 at ground potential,the latter line being common to the two cells. The conductive lines 6and 8 are for example metal lines that are separated from subjacentlayers by an insulator 9, shown in FIG. 2B, and connected to chosenregions by conductive vias and optionally conductive tracks (not shown).

The two cells C1, C2 share the same well 25, which is doped n-type andformed in a substrate 26 that is doped p-type. A trench 27 is formedbetween the two cells, in the well 25. The trench 27 extends, under theconductive line 8, at least the entire width of the well 25, but to adepth that is smaller than the depth of the well 25, as may be seen inFIG. 2B. The portion of the well 25 of the cell C1 and the portion ofthe well 25 of the cell C2 are connected by a section of the well 25,this section being located under the trench 27. The trench 27 has aconductive core, for example made of polysilicon 29, separated from thewell 25 by a dielectric cladding 30, for example made of silicon oxide.

The n-doped well 25 is covered with a highly n-doped layer 32. A contact34, 35 is formed on each of the two portions of the layer 32, i.e., thetwo portions separated by the trench 27. A contact 36 connects the core29 of the trench 27 to the conductive line 8, which is at the referencepotential GND.

Provision is made here, intermittently, for example periodically, forthe contacts 34 and 35 to be used to check the continuity of the well 25between the two cells, for example by measuring the impedance betweenthe two contacts, which is compared to a reference value. To do this,the contacts 34 and 35 are connected to a circuit 80 (FIG. 5) capable,intermittently, of taking a measurement, for example a measurement of acurrent flowing through the well 25 between the contacts 34 and 35,which thereby provides an indirect measurement of the impedance betweenthe two contacts.

During a back-side attack such as described above, targeting such cells,the pirate etches, from the back side, into the well 25. The bottom ofthe trench 27 is approached and for example reached. This will cause avariation in the impedance between the nodes corresponding to thecontacts 34 and 35, which will be able to be measured during asubsequent measurement. The measurements of the impedance between thecontacts 34 and 35 are sufficiently close together to allow rapiddetection of a back-side attack.

In the cells C1 and C2, which are protected from attacks as wasindicated above, entirely conventional capacitors will possibly beformed. However, given that the cell already comprises a trenchisolation 27, it is desirable, to minimize the number of fabricatingsteps, to form these capacitors in trench isolations 40 and 41 of thesame type as the separating trench 27 between the cells. Thus, as may beseen in the top view of FIG. 2A, these trenches 40 and 41 cross thetrench 27 and their internal conductive cores are common. The core ofthe trench 27 is therefore also a capacitor element.

In normal operation, the p-substrate 26 will be biased to a potentialGND, the n-well 25 to a potential VDD and the conductor of the core 29of the trenches 27, 40 and 41 to a potential GND. As is shown, thetrenches 40 and 41 extend the length of the two cells and are preferablyidentical to the trench 27.

It will again be noted that, whereas, in normal operation, the well 25common to the two cells C1 and C2 is at a single potential, VDD, duringphases of detecting whether an attack is being carried out, the two wellportions are for example placed at different potentials in order todetect the impedance between the contacts 34 and 35.

Above, in a general and simplified way, a pair of adjacent cellscontaining capacitors arranged so as to detect an attack was described.It will be shown below that not only, as was described above, is thisarrangement effective, but furthermore a practical structure allowingthis arrangement to be used is particularly simple to produce.

FIG. 3 shows an example, with dimensions labelled, of anintegrated-circuit cell produced in a particular technology. The cell,C3, is formed between two conductive lines 6 and 8 having widths of 0.12μm, which are at VDD and GND, respectively. The cell is encircled by ashallow trench isolation 50 (commonly called an STI in the art). Thecell contains an n-well 51 formed in a p-substrate 52. The n-well 51 isencircled by an STI insulating wall 53. In the example considered here,the distance between the two conductive lines is 1.02 μm. The lateraldimension of the n-well 51, in the direction parallel to the conductivelines 6 and 8, is 0.57 μm and the distance, in the same direction,between the well 51 and the sides of the cell C3 is 0.34 μm.

FIGS. 4A to 4D show one example embodiment of two capacitor cellsprotected from back-side attacks and having a high total capacitancewith regard to the available cell real estate and existing fabricationtechnologies. FIG. 4A is a top view, with dimensions labelled, and FIGS.4B to 4D are cross-sectional views along the lines B-B, C-C and D-D ofFIG. 4A.

As FIGS. 4A to 4D illustrate, in one embodiment two adjacent cells C4and C5 are used, the cells being located on either side of a conductiveline 8 at the reference voltage GND and between conductive lines 6 atthe reference voltage VDD. The horizontal dimensions of the structureare those illustrated in FIG. 3. An n-well 25, which is encircled by anSTI trench isolation 61, extends in both the two cells in the way shown.The upper limit of the well 25 is located 0.34 μm from the closestconductive line 6, and its lower limit is located at the same distancefrom the other conductive line 6. The well 25 is formed in a p-typesubstrate 26. As was described with reference to FIGS. 2A and 2B, atrench isolation 27 extends in the n-well 25 under the conductive line 8at GND. In this structure, it is possible to place, vertically in theinterior of the n-well 25, three trench isolations 64, 65 and 66 havingwidths of about 0.16 μm, this being perfectly compatible with the designrules of the technology considered here. One of the trenches 64, 65 and66 has a length smaller than that of the other trenches, so as to allowmeasurement contacts 34 and 35 to be formed on a highly n-doped layer 32formed on the well 25, such as was described with reference to FIGS. 2Aand 2B. Likewise, on the periphery of the n-well 25, it is possible toplace, in the p-substrate 26, trenches connected to a conductive line 6,said trenches being insulated from the p-doped substrate 26 and thehighly p-doped layer, and discontinuous between the upper portionthereof, 70 on the upper side, and the lower portion thereof, 71 on thelower side. Once again, the production of trenches of the width of about0.16 μm is perfectly compatible with the design rules of the technologyconsidered here.

FIGS. 4B, 4C and 4D, which are respectively cross-sectional views alongthe lines B-B, C-C and D-D of FIG. 4A, allow the production of thestructure to be better understood. These figures will not be describedin detail because they are self-explanatory. The various elements ofthese figures have been referenced by the same references as in FIG. 4Aand, where appropriate, as in FIGS. 2A and 2B. The presence ofmeasurement contacts 34 and 35 will in particular be noted. The hatchedregions correspond to STI insulating walls.

The objective of the description of FIG. 4A and the presence of FIGS.4B, 4C and 4D is to show that the structure described here isparticularly simple to produce in one practical case. Of course,depending on the technology and the design rules in question, variousother embodiments could be used. In any case, practical production willbe simple.

In the particular case shown in FIGS. 4A to 4D, not only is a capacitorhaving a capacitance of 10 pF obtained for a pair of cells, this being aparticularly high value for the small amount of silicon real estateused, but also decoupling-capacitor cells that are protected from aback-side attack.

The various embodiments described above can be combined to providefurther embodiments. These and other changes can be made to theembodiments in light of the above-detailed description. In general, inthe following claims, the terms used should not be construed to limitthe claims to the specific embodiments disclosed in the specificationand the claims, but should be construed to include all possibleembodiments along with the full scope of equivalents to which suchclaims are entitled. Accordingly, the claims are not limited by thedisclosure.

1. A decoupling capacitor comprising: first and second capacitor cellssharing a well with each other; a first trench isolation passing throughthe well between the two cells without reaching a bottom of the well;and first and second conductive contacts respectively connected to thefirst and second capacitor cells.
 2. The decoupling capacitor accordingto claim 1, further comprising conductive first and second lateralsupply strips and a conductive central supply strip, wherein the firstcapacitor cell is positioned between the first lateral supply strip andthe central supply strip and the second capacitor cell is positionedbetween the second lateral supply strip and the central supply strip. 3.The decoupling capacitor according to claim 2, wherein the first trenchisolation includes a conductive core and a dielectric cladding thatsurrounds the conductive core and insulates the conductive core from thewell, the central supply strip being electrically coupled to theconductive core.
 4. The decoupling capacitor according to claim 1,further comprising second trench isolations extending longitudinally inthe well in a direction orthogonal to a longitudinal extension of thefirst trench isolation.
 5. The decoupling capacitor according to claim1, further comprising: a substrate in which the well is formed; a thirdcapacitor cell including a second trench isolation formed in thesubstrate and outside of the well; and a fourth capacitor cell includinga third trench isolation formed in the substrate and outside of thewell.
 6. The decoupling capacitor according to claim 5, wherein thesecond trench isolation encircles three sides of a first half of thewell and the third trench isolation encircles three sides of a secondhalf of the well.
 7. The decoupling capacitor according to claim 5,wherein each of the second and third trench isolations includes aconductive core and a dielectric cladding that surrounds the conductivecore and insulates the conductive core from the substrate.
 8. Thedecoupling capacitor according to claim 5, further comprising a shallowtrench insulation that completely encircles the well and separates thesecond and third trench isolations from the well.
 9. An integratedcircuit comprising: a decoupling capacitor that includes: first andsecond capacitor cells sharing a well with each other; a first trenchisolation passing through the well between the two cells withoutreaching a bottom of the well; and first and second conductive contactsrespectively connected to the first and second capacitor cells; and adetection circuit configured to detect an impedance between the firstand second contacts.
 10. The integrated circuit according to claim 9,wherein the decoupling capacitor includes conductive first and secondlateral supply strips and a conductive central supply strip, wherein thefirst capacitor cell is positioned between the first lateral supplystrip and the central supply strip and the second capacitor cell ispositioned between the second lateral supply strip and the centralsupply strip.
 11. The integrated circuit according to claim 10, whereinthe first trench isolation includes a conductive core and a dielectriccladding that surrounds the conductive core and insulates the conductivecore from the well, the central supply strip being electrically coupledto the conductive core.
 12. The integrated circuit according to claim 9,wherein the decoupling capacitor includes second trench isolationsextending longitudinally in the well in a direction orthogonal to alongitudinal extension of the first trench isolation.
 13. The integratedcircuit according to claim 9, wherein the decoupling capacitor includes:a substrate in which the well is formed; a third capacitor cellincluding a second trench isolation formed in the substrate and outsideof the well; and a fourth capacitor cell including a third trenchisolation formed in the substrate and outside of the well.
 14. Theintegrated circuit according to claim 13, wherein the second trenchisolation encircles three sides of a first half of the well and thethird trench isolation encircles three sides of a second half of thewell.
 15. The integrated circuit according to claim 13, wherein each ofthe second and third trench isolations includes a conductive core and adielectric cladding that surrounds the conductive core and insulates theconductive core from the substrate.
 16. The integrated circuit accordingto claim 13, further comprising a shallow trench insulation thatcompletely encircles the well and separates the second and third trenchisolations from the well.
 17. A method of using a decoupling capacitorthat includes first and second capacitor cells sharing a well with eachother; a first trench isolation passing through the well between the twocells without reaching a bottom of the well; and first and secondconductive contacts respectively connected to the first and secondcapacitor cells, the method comprising: setting the first and secondconductive contacts to first and second voltages, respectively, thefirst and second voltages being different from each other; and measuringan impedance across the well while the first and second conductivecontacts are set at the first and second voltages, respectively.
 18. Themethod according to claim 17, wherein the decoupling capacitor includesconductive first and second lateral supply strips and a conductivecentral supply strip, wherein the first capacitor cell is positionedbetween the first lateral supply strip and the central supply strip andthe second capacitor cell is positioned between the second lateralsupply strip and the central supply strip, the method includingproviding a first supply voltage to the first and second lateral supplystrips and a second supply voltage to the central supply strip.
 19. Themethod according to claim 18, wherein the first trench isolationincludes a conductive core and a dielectric cladding that surrounds theconductive core and insulates the conductive core from the well, thecentral supply strip being electrically coupled to the conductive core,wherein applying the second supply voltage to the central supply stripalso supplies the second supply voltage to the conductive core.